A 3.3fJ/conversion-step 250kS/s 10b SAR ADC using optimized vote allocation

This paper presents a 10b successive approximation register (SAR) analog-to-digital converter (ADC) that operates at 0.5V supply voltage and supports a flexible differential input dynamic range from 0.4V to 1V. The proposed ADC employs a majority vote comparison along with a non-binary architecture to alleviate the effect of comparator noise in scaled input voltage swings. To maximize performance subject to comparator power level constraints, the allocation of votes is optimized for each bit cycle. The prototype, fabricated in 65nm CMOS process, achieves ENOB ranging from 7.1b to 9.1b and FOM from 3.3 to 6.8fJ/conversion step while operating at 250kS/s.