Title :
An embedded real-time SIMD processor array for image processing
Author :
Andrews, David ; Kancler, Cliff ; Wealand, Barry
Author_Institution :
Arkansas Univ., USA
Abstract :
The paper presents an overview of the SuperSPAR (Systolic Processor Array) architecture and chip set. The SuperSPAR was designed by Lockheed Martin to bring the benefits of massively parallel SIMD processing to the embedded systems domain. The system philosophy focused on building a hierarchy of scaleable subarray modules allowing systems to be configured by “plugging together” any number of these modules to meet specific system requirements. A typical SPAR system consists of three primary components: 1) a scalar processor board containing a scalar processor, local RAM, program ROM, a host I/O interface, and an Sbus interface, 2) a SPAR controller board which contains the SPAR´s instruction and global memory, a transformer/splitter, an instruction queue, and a microcode sequencer, and 3) a SPAR array board which contains some number of interconnected SuperSPAR chips and their associated off-chip local data memories
Keywords :
digital signal processing chips; memory architecture; real-time systems; system buses; systolic arrays; SPAR controller board; Sbus interface; SuperSPAR architecture; SuperSPAR chip set; embedded real-time SIMD processor array; embedded systems; global memory; host I/O interface; image processing; instruction; instruction queue; local RAM; massively parallel SIMD processing; microcode sequencer; program ROM; scalar processor; scalar processor board; scaleable subarray module hierarchy; splitter; system requirements; systolic processor array; transformer; Buildings; Computer architecture; Control systems; Embedded system; Image processing; Random access memory; Read only memory; Read-write memory; Real time systems; Systems engineering and theory;
Conference_Titel :
Parallel and Distributed Real-Time Systems, 1996. Proceedings of the 4th International Workshop on
Conference_Location :
Honolulu, HI
Print_ISBN :
0-8186-7515-2
DOI :
10.1109/WPDRTS.1996.557646
