Title :
Lithography friendly routing: From construct-by-correction to correct-by-construction
Author :
Pan, David Z. ; Cho, Minsik ; Yuan, Kun ; Ban, Yongchan
Author_Institution :
Dept. of ECE, Univ. of Texas at Austin, Austin, TX, USA
Abstract :
Deep sub-wavelength lithography, i.e., using the 193 nm lithography to print 45 nm, 32 nm, and possibly 22 nm integrated circuits, is one of the most fundamental limitations for the continuous CMOS scaling. Lithography printability is strongly layout dependent, thus routing plays an important role in addressing the overall circuit manufacturability and product yield since it is the last major physical design step before tape out. This paper will discuss some recent advancement of lithography friendly routing from post-routing hotspot fixing (construct- by-correction) to during-routing hotspot avoidance (correct-by- construction) guided by various lithography metrics. We will compare these approaches, and show how to combine them. We will also discuss the emerging research needs in lithography friendly routing, such as double patterning lithography and next-generation-lithography.
Keywords :
CMOS integrated circuits; integrated circuit design; lithography; network routing; construct-by-correction; continuous CMOS scaling; correct-by-construction; deep sub-wavelength lithography; double patterning lithography; lithography friendly routing; lithography printability; overall circuit manufacturability; post-routing hotspot fixing; size 193 nm; size 22 nm; size 32 nm; size 45 nm; Central Processing Unit; Lithography; Logic design; Manufacturing industries; Optical noise; Photonic integrated circuits; Routing; Runtime; Timing; Very large scale integration;
Conference_Titel :
Solid-State and Integrated-Circuit Technology, 2008. ICSICT 2008. 9th International Conference on
Conference_Location :
Beijing
Print_ISBN :
978-1-4244-2185-5
Electronic_ISBN :
978-1-4244-2186-2
DOI :
10.1109/ICSICT.2008.4735031
