DocumentCode
2155374
Title
Distributed clock generator for synchronous SoC using ADPLL network
Author
Zianbetov, Eldar ; Galayko, Dimitri ; Anceau, Francois ; Javidan, M. ; Shan, Chan ; Billoint, O. ; Korniienko, A. ; Colinet, E. ; Scorletti, G. ; Akrea, J.M. ; Juillard, Jerome
Author_Institution
LIP6 Lab., UPMC, Paris, France
fYear
2013
fDate
22-25 Sept. 2013
Firstpage
1
Lastpage
4
Abstract
This paper presents a novel architecture of on-chip clock generation employing a network of oscillators synchronized by the distributed all-digital PLLs (ADPLLs). The implemented prototype has 16 clocking domains operating synchronously in a frequency range of 1.1-2.4 GHz. The synchronization error between the neighboring clock domains is less than 60 ps. The fully digital architecture of the generation offers flexibility and efficient synchronization control suitable for use in synchronous SoCs.
Keywords
clocks; digital phase locked loops; oscillators; synchronisation; system-on-chip; ADPLL network; all-digital PLL; distributed clock generator; on-chip clock generation; oscillators; synchronization error; synchronous SoC; Clocks; Oscillators; Phase frequency detector; Phase locked loops; Synchronization; System-on-chip; Tuning;
fLanguage
English
Publisher
ieee
Conference_Titel
Custom Integrated Circuits Conference (CICC), 2013 IEEE
Conference_Location
San Jose, CA
Type
conf
DOI
10.1109/CICC.2013.6658437
Filename
6658437
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