On parallelization of neural classification algorithms

Since the mid 80´s neural computing has been gaining substantial attention as an important computing paradigm. A variety of neural computation models and learning algorithms have been developed and implemented on both general-purpose computers and dedicated hardware. The spectacular advances in VLSI technology over the last few years has further sparked interest and research activities in the field. This paper examines the implementation of neural classification algorithms, the main theme is focused on the parallelisation of a novel neural classifier architecture on three different platforms including the latest on-chip ZISC036 “hyperparallel” neuro-processors. A significant advantage of implementing neural networks directly on silicon is that it overcomes performance limitations of complex networks required for real-time applications. Furthermore, the technology owes much to its efficacy in achieving an algorithmic match between the fine-grained, parallel computation structure of neural architectures and the highly regular VLSI processing model