Optimality analysis for power/ground grid automatic generation in early design stage

As the number of on die transistors continues to increase, whether it is possible to generate a near optimum P/G grid automatically in early design stage will significantly affects design closure. In this paper, optimal conditions for P/G grid automatic generation are discussed. We prove that for regular grid, there does not exist a global optimal point at which both metal usage and maximal voltage drop can be minimized. Also, an efficient algorithm is proposed to generate Pareto optimal P/G grid. Experimental results show that the proposed algorithm is more efficient than the classical wire sizing strategy.