Title :
Synthesis and characterization of high quality ultrathin gate oxides for VLSI/ULSI circuits
Author :
Roy, P.K. ; Diklan, R.H. ; Martin, E.P. ; Shive, S.F. ; Sinha, Arun Kumar
Author_Institution :
AT&T Bell Lab., Allentown, PA, USA
Abstract :
A major hurdle in VLSI/ULSI technology has been the inability to grow ultrathin oxides with low defect and interface trap densities and to generate a planar stress-free silicon/silicon-dioxide (Si/SiO/sub 2/) interface. The authors describe the fabrication of thin multilayered stacked SiO/sub 2/ structure with such qualities. A huge improvement in the quality of these stacked oxides has been achieved through a novel synthesis of a three-step process which involves growing, depositing, and growing SiO/sub 2/ layers on silicon substrates by thermal oxidation, chemical vapor deposition, and densification/oxidation, respectively. These oxides have the ideal combination of low defect and interface trap densities, and the Si/SiO/sub 2/ interface generated during the synthesis is structurally superior.<>
Keywords :
VLSI; chemical vapour deposition; dielectric thin films; insulating thin films; integrated circuit technology; metal-insulator-semiconductor structures; oxidation; semiconductor technology; semiconductor-insulator boundaries; silicon compounds; 150 A; CVD; ULSI; VLSI; characterization; chemical vapor deposition; densification; fabrication; gate dielectrics; high quality ultrathin gate oxides; low defect density; low interface trap density; stacked oxides; stressfree Si-SiO/sub 2/ interface; synthesis; thermal oxidation; thin multilayered stacked SiO/sub 2/ structure; three-step process; Annealing; Chemical vapor deposition; Circuit synthesis; Dielectrics; Fabrication; Oxidation; Random access memory; Silicon; Ultra large scale integration; Very large scale integration;
Conference_Titel :
Electron Devices Meeting, 1988. IEDM '88. Technical Digest., International
Conference_Location :
San Francisco, CA, USA
DOI :
10.1109/IEDM.1988.32912