Title :
Charge steering: A low-power design paradigm
Author_Institution :
Electr. Eng. Dept., Univ. of California, Los Angeles, Los Angeles, CA, USA
Abstract :
Discrete-time charge-steering circuits consume less power than their continuous-time current-steering counterparts even at high speeds. This advantage can be exploited in the design of semi-analog circuits such as latches, demultiplexers, and CDR circuits as well as mixed-mode systems such as ADCs. Employing charge steering in 65-nm CMOS technology, a 25-Gb/s CDR/deserializer consumes 5 mW and a 10-bit 800-MHz pipelined ADC draws 19 mW.
Keywords :
CMOS integrated circuits; analogue-digital conversion; clock and data recovery circuits; low-power electronics; CDR; CMOS technology; bit rate 25 Gbit/s; charge steering; clock and data recovery; deserializer circuit; discrete-time charge-steering circuits; low-power design; pipelined ADC; power 19 mW; power 5 mW; semianalog circuits; size 65 nm; Capacitance; Capacitors; Clocks; Latches; Optical signal processing; Topology; Voltage-controlled oscillators;
Conference_Titel :
Custom Integrated Circuits Conference (CICC), 2013 IEEE
Conference_Location :
San Jose, CA
DOI :
10.1109/CICC.2013.6658443
