Design of sample-and-hold amplifiers for high-speed low-voltage A/D converters

Multi-step analog-to-digital converters typically employ a sample-and-hold amplifier at the front end that must achieve high speed and high linearity with low power dissipation. Furthermore, sampling circuits can be used to alleviate the timing and bandwidth limitations of one-step converters such as flash and interpolative architectures. This paper describes design techniques for sample-and-hold circuits utilized in high-speed low-voltage data converters, Following a review of the role of sampling in various converter architectures, two broad categories of sampling techniques are introduced and properties of basic analog switches are summarized. Next, conventional sampling architectures are discussed, design methods for CMOS, bipolar, and BiCMOS implementations are studied, and several examples embodying these methods are presented. Finally, characterization of high-speed sampling circuits is described