An efficient thermal optimization flow using incremental floorplanning for 3D microprocessors

To eliminate hotspots in 3D designs, physical layouts are always adjusted by shifting hot blocks. However, these modifications may degrade the packing area as well as microprocessor performance greatly. Furthermore, to improve time-to-market via design cycle reduction, incremental design must move from an expert methodology to a mainstream design methodology: one that is automated, integrated, reliable, and repeatable. To avoid random incremental modification, which may be inefficient and need long runtime to converge, in this paper, potential gain is modeled for each candidate incremental change. Based on the potential gain, a novel thermal optimization flow to intelligently choose the best incremental operation is presented. Experimental results show that the thermal optimization flow can reduce max on-chip temperature by 34% while performance of the design is still maintained.