A sub-50 ps single poly planar bipolar technology

Author

Chen, T.C. ; Tang, D.D. ; Chuang, C.T. ; Cressler, J.D. ; Warnock, J. ; Li, G.P. ; Biolsi, P.E. ; Danner, D.A. ; Polcari, M.R. ; Ning, T.H.

Author_Institution

IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA

fYear

1988

fDate

11-14 Dec. 1988

Firstpage

740

Lastpage

743

Abstract

The authors present a single-poly bipolar technology using an advanced transistor with an LDD (lightly doped drain)-like self-aligned lateral profile. The device is isolated by a silicon-filled deep trench with a collector-to-collector breakdown voltage of 33 V, and the field oxide is provided by a low-temperature breakless process. The integrated process yields a structure with minimal topography, thereby avoiding several serious concerns associated with the conventional double-poly structures. Using this technology, sub-50-ps ECL (emitter coupled logic) circuits have been realized, demonstrating for the first time the potential of the single-poly device.<>

Keywords

bipolar integrated circuits; elemental semiconductors; emitter-coupled logic; integrated circuit technology; integrated logic circuits; semiconductor technology; silicon; 33 V; 50 ps; ECL; LDD-like profile; collector-to-collector breakdown voltage; emitter coupled logic; field oxide; integrated process; low-temperature breakless process; minimal topography; self-aligned lateral profile; semiconductors; single poly planar bipolar technology; single polycrystalline Si; single-poly device; trench isolation; Breakdown voltage; Circuit optimization; Furnaces; Implants; Integrated circuit technology; Isolation technology; Rapid thermal annealing; Shadow mapping; Surface resistance; Surface topography;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 1988. IEDM '88. Technical Digest., International

Conference_Location

San Francisco, CA, USA

ISSN

0163-1918

Type

conf

DOI

10.1109/IEDM.1988.32918

Filename

32918