Title :
A 28nm high density 1R/1W 8T-SRAM macro with screening circuitry against read disturb failure
Author :
Yabuuchi, M. ; Fujiwara, H. ; Tsukamoto, Yuya ; Tanaka, Mitsuru ; Tanaka, Shoji ; Nii, Koji
Author_Institution :
Renesas Electron. Corp., Kodaira, Japan
Abstract :
We developed a high density 1R/1W SRAM macro based on 8T-SRAM with an effective scheme for Design for Testability. To achieve a smaller Macro area, a differential sense amplifier is introduced to read the data, where the reference voltage for reading 0/1 data is generated by unselected cell array. In addition, we proposed a screening test circuit for read disturb operation. A 512 kbit two port SRAM macro based upon 28nm process was designed, confirming experimentally that the worst minimum operation voltage (Vmin) can be reproduced by our test circuit. The bit density of 3.16 Mb/mm2 was achieved, which is the highest among recent literatures.
Keywords :
SRAM chips; design for testability; differential amplifiers; integrated circuit reliability; integrated circuit testing; two-port networks; design for testability; differential sense amplifier; high density 1R-1W 8T-SRAM macro; memory size 512 KByte; read disturb failure; screening test circuit; size 28 nm; two port SRAM macro; Capacitance; Circuit stability; Clocks; Computer architecture; Degradation; Ports (Computers); Random access memory; 1R/1W SRAM; 8T-SRAM; Disturb failure; High density; Screening test circuit;
Conference_Titel :
Custom Integrated Circuits Conference (CICC), 2013 IEEE
Conference_Location :
San Jose, CA
DOI :
10.1109/CICC.2013.6658451
