Title :
A sub-30 psec Si bipolar LSI technology
Author :
Gomi, T. ; Miwa, H. ; Sasaki, H. ; Yamamoto, H. ; Nakamura, M. ; Kayanuma, A.
Author_Institution :
Sony Corp., Kanagawa, Japan
Abstract :
The authors describe an extremely-high-speed bipolar LSI technology. It uses 0.8- mu m-rule polysilicon emitter-base self-aligned, shallow-junction, and trench-isolation technologies. An LCML circuit with a minimum propagation delay time of 24 ps/gate has been realized at a gate current of 2.2 mA. The maximum cutoff frequency of the transistor is 30 GHz. The key process of the high-speed transistor is the shallow-junction technology, using polysilicon double diffusion, a lightly doped ´link´ base, collector ion implantation, and rapid thermal annealing. By using the lightly doped shallow ´link´ region the degradation of BV/sub EBO/ and cutoff frequency can be avoided.<>
Keywords :
bipolar integrated circuits; elemental semiconductors; emitter-coupled logic; integrated circuit technology; integrated logic circuits; large scale integration; semiconductor technology; silicon; 0.8 micron; 2.2 mA; 24 to 30 ps; 30 GHz; LCML circuit; bipolar LSI technology; collector ion implantation; current mode logic; cutoff frequency; gate current; high-speed transistor; key process; lightly doped link base; polycrystalline Si; polysilicon double diffusion; polysilicon emitter-base; propagation delay time; rapid thermal annealing; self-aligned; semiconductors; shallow-junction; shallow-junction technology; submicron; trench-isolation; Circuits; Delay; Electrodes; Impurities; Ion implantation; Isolation technology; Large scale integration; Lithography; Rapid thermal annealing; Rapid thermal processing;
Conference_Titel :
Electron Devices Meeting, 1988. IEDM '88. Technical Digest., International
Conference_Location :
San Francisco, CA, USA
DOI :
10.1109/IEDM.1988.32919
