• DocumentCode
    2155844
  • Title

    A HKMG 28nm 1GHz fully-pipelined tile-able 1MB embedded SRAM IP with 1.39mm2 per MB

  • Author

    Ming-Zhang Kuo ; Takahashi, Osamu ; Ping-Lin Yang ; Cheng-Chung Lin ; Min-Jer Wang ; Ping-Wei Wang ; Sang-Hoo Dhong

  • Author_Institution
    Design Technol. Platform, Taiwan Semicond. Manuf. Co., Hsinchu, Taiwan
  • fYear
    2013
  • fDate
    22-25 Sept. 2013
  • Firstpage
    1
  • Lastpage
    4
  • Abstract
    A fully-pipelined tile-able 1MB SRAM IP with a 0.127um2 cell in a HKMG 28nm bulk technology has an area of 1.39mm2/MB with 79.2% array efficiency. It operates with 2-cycle latency up to 1GHz. The no-repair hardware has a circuit limited yield of 99.92 and 53% at 100 and 850MHz, respectively with 0.75V VDD. A Data Retention Voltage of 0.42V has been measured.
  • Keywords
    SRAM chips; HKMG technology; SRAM IP; data retention voltage; frequency 1 GHz; high-K metal gate technology; no-repair hardware; size 28 nm; Arrays; Current measurement; IP networks; Leakage currents; SRAM cells; Semiconductor device measurement; 28nm; SRAM; eDRAM;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Custom Integrated Circuits Conference (CICC), 2013 IEEE
  • Conference_Location
    San Jose, CA
  • Type

    conf

  • DOI
    10.1109/CICC.2013.6658452
  • Filename
    6658452
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2155844