A 1.8mW 2MHz-BW 66.5dB-SNDR ΔΣ ADC using VCO-based integrators with intrinsic CLA

This paper presents a scaling-friendly continuous-time closed-loop VCO-based ΔΣ ADC. It uses the VCO as both quantizer and integrator, and thus, obviates the need for power-hungry scaling-unfriendly OTAs and precision comparators. It arranges two VCOs in a pseudo-differential manner, which cancels out even-order distortions. More importantly, it brings an intrinsic clocked averaging (CLA) capability that automatically addresses DAC mismatches. The prototype ADC in 130nm CMOS occupies a small area of 0.03mm² and achieves 66.5dB SNDR over 2MHz BW while sampling at 300MHz and consuming 1.8mW under a 1.2V power supply. It can also operate with a low analog supply of 0.7V and achieves 65.8dB SNDR while consuming 1.1mW. The corresponding figure-of-merits (FOMs) for the two cases are 0.25pJ/step and 0.17pJ/step respectively.