An 8-bit 1-GHz digital to analog converter using 0.5 mu m gate inverted HEMTs

Author

Seki, S. ; Saito, T. ; Fujishiro, H.I. ; Nishi, S. ; Sano, Y.

Author_Institution

Oki Electr. Ind. Co. Ltd., Tokyo, Japan

fYear

1988

fDate

11-14 Dec. 1988

Firstpage

770

Lastpage

773

Abstract

The design and performance of a monolithic 8-bit digital-to-analog converter (DAC) are described. The DAC consists of a segmented DAC for the upper 2 bits and an R-2R ladder network for the lower 6 bits. The chip has been fabricated using 0.5- mu m-gate inverted HEMTs (high electric mobility transistors). The DC linearity of the DAC is better than 0.18 LSB without trimming. This accuracy corresponds to a precision of 9.5 bits. The results show a 10%/-90% risetime of 170 ps, a fall time of 100 ps, and settling time to 1% of 0.9 ns. The operation of the DAC was verified at a clock rate of 1.2 GHz.<>

Keywords

digital-analogue conversion; field effect integrated circuits; high electron mobility transistors; 0.5 micron; 0.9 ns; 1 to 1.2 GHz; 100 ps; 170 ps; 8 bit; DC linearity; R-2R ladder network; clock rate; fall time; high electric mobility transistors; inverted HEMTs; monolithic D/A convertor; risetime; segmented DAC; settling time; submicron gate; Artificial intelligence; Circuit synthesis; Clocks; Digital-analog conversion; FETs; Fabrication; HEMTs; MODFETs; Switches; Threshold voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 1988. IEDM '88. Technical Digest., International

Conference_Location

San Francisco, CA, USA

ISSN

0163-1918

Type

conf

DOI

10.1109/IEDM.1988.32925

Filename

32925