High voltage pullup devices in a BiMOS HVIC technology

Author

Scott, R.S. ; Pattanayak, D.N. ; Kohl, J.E. ; Adler, M.S. ; Ahle, R.S. ; Wildi, E.J.

Author_Institution

Gen. Electr. Co., Schenectady, NY, USA

fYear

1988

fDate

11-14 Dec. 1988

Firstpage

800

Lastpage

803

Abstract

High-voltage complementary pullup and pulldown devices have been fabricated in a high-voltage integrated circuit process that is based on thin epitaxial layers (<10 mu m). The device structures described allow high-voltage pullup devices to be realized where normally only pulldown devices would be possible in such thin epitaxial layers. Only one additional mask was needed to incorporate these devices into the existing junction-isolated BiMOS technology. A 400-V chip featuring in high-voltage, low-power consumption drivers along with 5-V CMOS logic has been fabricated using novel depletion-mode NMOS design.<>

Keywords

BIMOS integrated circuits; integrated circuit technology; power integrated circuits; 10 micron; 400 V; 5-V CMOS logic; BiMOS HVIC technology; HV chip; depletion-mode NMOS design; high-voltage integrated circuit process; high-voltage pullup devices; low-power consumption drivers; thin epitaxial layers; Avalanche breakdown; Driver circuits; Epitaxial layers; Integrated circuit technology; Isolation technology; MOS devices; Research and development; Substrates; Switches; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 1988. IEDM '88. Technical Digest., International

Conference_Location

San Francisco, CA, USA

ISSN

0163-1918

Type

conf

DOI

10.1109/IEDM.1988.32932

Filename

32932