Technological design rules for control circuits of static power converters

The study goal is the characterization of the self-disturbance of static power converters through the ground-plane. With the increasing integration scale of static power converters, power electronic components are located very close to signal components. Moreover, circuits are increasingly implanted on the same substrate. During the commutation of the semiconductors, high voltage rates appear to the power transistor, creating common mode currents which return through control elements and may disturb them. These common mode currents are generated by parasitic capacitances existing between ground-plane and circuit traces. Simulations can be used to characterize this kind of perturbation, but many simulations are needed before finding the good design of traces. A new approach is proposed to model the disturbance process in order to optimize the traces of circuits. This approach establishes a guide for technological design of the circuit without modifying the function of the system. A practical case is studied that allows the proposed design rules to be applied