A 10Gbps, 1.24pJ/bit, burst-mode clock and data recovery with jitter suppression

Author

Ming-Chiuan Su ; Wei-Zen Chen ; Pei-Si Wu ; Yu-Hsian Chen ; Chao-Cheng Lee ; Shyh-Jye Jou

Author_Institution

Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan

fYear

2013

fDate

22-25 Sept. 2013

Firstpage

1

Lastpage

4

Abstract

A 10Gbps, 1/5-rate burst mode clock and data recovery (BMCDR) circuit is proposed. The BMCDR is reconfigurable between data gating mode and phase tracking mode to achieve instantaneous phase-locking with jitter suppression for 10 GPON. Incorporating a 1/5-rate CDR with 1:5 demultiplexer, it achieves a high energy efficiency of 1.24pJ/bit. With a 4MHz, 0.22UI_pp input data jitter, the recovered clock jitter at 2GHz is 2.94ps_rms. The prototype chip is fabricated in UMC 55nm CMOS technology. Chip size is 200×150μm².

Keywords

CMOS digital integrated circuits; clock and data recovery circuits; jitter; passive optical networks; BMCDR circuit; GPON; UMC CMOS technology; bit rate 10 Gbit/s; burst-mode clock and data recovery circuit; data gating mode; demultiplexer; energy efficiency; frequency 2 GHz; frequency 4 MHz; gigabit passive optical network; input data jitter; instantaneous phase-locking; jitter suppression; phase tracking mode; recovered clock jitter; size 55 nm; time 2.94 ps; CMOS integrated circuits; Clocks; Computer architecture; Detectors; Jitter; Logic gates; Phase locked loops;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference (CICC), 2013 IEEE

Conference_Location

San Jose, CA

Type

conf

DOI

10.1109/CICC.2013.6658469

Filename

6658469