Modeling of a digitally assisted 14-bit 100MSample/s pipelined ADC using open-loop residue amplification

A novel digitally assisted high-speed 14-bit pipelined ADC model based on matlab/simulink is proposed. The model consists of a 4-bit first-stage with nonlinearity gain error, a 2-bit second-stage with 1-bit redundancy and five ideal 2-bit stages. A backend calibration technique is used to calibrate the nonlinearity error of the first stage, which significantly improves the Signal Noise Ratio (SNR) and Effective Number of Bit (ENOB) of the Analog-to-Digital Converter (ADC). Simulation results indicate that the maximum SNR and ENOB of this pipeline ADC reach the value of 82dB and 14 bits respectively under the case of the input signal frequency at 9.72MHz and the sampling clock at 100MHz after calibration.