An insulated gate bipolar transistor with a self-aligned DMOS structure

Author

Mori, M. ; Nakano, Y. ; Tanaka, T.

Author_Institution

Hitachi Ltd., Ibaraki-ken, Japan

fYear

1988

fDate

11-14 Dec. 1988

Firstpage

813

Lastpage

816

Abstract

The authors describe a high-performance insulated-gate bipolar transistor (IGBT) with a self-aligned double-diffused MOS (DMOS) structure (SADMOS). A phosphosilicate glass (PSG) sidewall is used to form the n/sup +/ layer and isolate the gate from the emitter electrode. The DMOS structure, including the 5- mu m gap between the polysilicon gates and the small p-layer region under the n/sup +/ layer, is thus fabricated with a completely self-aligned (SA) process. An SA DMOS IGBT with a breakdown voltage of 500 V had a forward voltage drop of 1.6 V at a forward current density of 1100 A/cm/sup 2/, a fall time of 0.2 mu s and dynamic latching current density of 100 A/cm/sup 2/. The forward voltage drop is reduced by 1/3 over that of an IGBT with a conventional DMOS structure.<>

Keywords

bipolar transistors; insulated gate field effect transistors; power transistors; 0.2 mus; 1.6 V; 500 V; IGBT; P2O5-SiO2; PSG sidewall; SADMOS; breakdown voltage; double-diffused MOS; dynamic latching current density; fall time; forward current density; forward voltage drop; insulated gate bipolar transistor; power transistor; self-aligned DMOS structure; Anisotropic magnetoresistance; Annealing; Boron; Current density; Dry etching; Electrodes; Fabrication; Insulated gate bipolar transistors; Silicon; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 1988. IEDM '88. Technical Digest., International

Conference_Location

San Francisco, CA, USA

ISSN

0163-1918

Type

conf

DOI

10.1109/IEDM.1988.32935

Filename

32935