Nonlinearity cancellation in digital PLLs (Invited paper)

One decade after their introduction into wireless applications, digital fractional-N phase-locked loops are becoming a competitive solution for products. Their ultimate level of spurs is often bounded by the resolution and the linearity of the time-to-digital converter. Although methods for mitigating its nonlinearity have been proven effective in lowering spurs, they typically increase the level of random noise. By contrast, digital-PLL architectures based on digital-to-time converters enable nonlinearity cancellation and spur reduction with no penalty on noise level, while reducing design complexity and power consumption.