Title :
Concurrent design of ESD protection and ICs for optimization and prediction
Author_Institution :
Dept. of Electr. Eng., Univ. of California, CA, USA
Abstract :
□ ESD failure is a killing factor to ICs □ On-chip ESD protection required for ICs □ Mixed-mode ESD design method for prediction □ ESD-IC co-design is important & feasible! □ Novel ESD design concept is the future.
Keywords :
electrostatic discharge; integrated circuit design; mixed analogue-digital integrated circuits; optimisation; ESD failure; ESD protection; IC; concurrent design; mixed-mode ESD design; optimization; Discharges (electric); Electromagnetic interference; Electrostatic discharges; Integrated circuits; Surge protection; Transient analysis;
Conference_Titel :
Custom Integrated Circuits Conference (CICC), 2013 IEEE
Conference_Location :
San Jose, CA
DOI :
10.1109/CICC.2013.6658502
