A 1/10000 lower error rate achievable SSD controller with Message-Passing Error Correcting Code architecture and Parity Area Combined scheme

Author

Kai Li ; Ito, Minora ; Esumi, Atsushi

Author_Institution

Siglead Inc., Yokohama, Japan

fYear

2013

fDate

22-25 Sept. 2013

Firstpage

1

Lastpage

3

Abstract

A new Error Correcting Code (ECC) solution aiming to improve the reliability of NAND flash memory (NAND) is proposed. Implemented in Solid-State Drive (SSD) controller IC (Fabricated in TSMC65LP), it is confirmed that more than 1/10000 lower error rate without increasing redundant bits (parity) of conventional BCH code, and 1.7x longer endurance of SSD can be achieved. This solution consists of two independent techniques: MP-ECC, a Message-Passing ECC architecture; and PAC, a Parity Area Combined ECC scheme.

Keywords

error correction codes; flash memories; integrated circuit reliability; MP-ECC; NAND flash memory reliability; PAC; SSD controller IC; TSMC65LP; error correcting code solution; error rate; message-passing ECC architecture; message-passing error correcting code architecture; parity area combined ECC scheme; parity area combined scheme; solid-state drive controller IC; Computer architecture; Decoding; Error analysis; Error correction codes; Flash memories; Parity check codes; Reliability;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference (CICC), 2013 IEEE

Conference_Location

San Jose, CA

Type

conf

DOI

10.1109/CICC.2013.6658520

Filename

6658520