Title :
A 2-V 3.7-mW delay locked-loop using recycling integrator correlators for a 5-Mcps DS-CDMA demodulator
Author :
Fujimoto, Yoshihisa ; Kawama, Shuichi ; Iizuka, Kunihiko ; Miyamoto, Masayuki ; Senderowicz, Daniel
Author_Institution :
Adv. Technol. Res. Labs., Sharp Corp., Nara, Japan
Abstract :
A Delay Locked-Loop (DLL) for a 5-Mcps DS-CDMA demodulator targeting IMT-2000 has been implemented consisting of six correlators, each one incorporating a form of ΔΣ modulation called recycling integrator to obtain a quantized correlation value between a received signal and PN sequence. The DLL can adapt to spreading ratios from 32 to 256 with an auxiliary ADC complementing the dynamic range degradation when the ratio is small. Fabricated in 0.35-μm double-metal double-poly CMOS process, the chip occupies 2.28 mm2 and dissipates 3.7 mW with a supply voltage of 2 V
Keywords :
CMOS integrated circuits; cellular radio; code division multiple access; correlators; delay lock loops; delta-sigma modulation; demodulators; mixed analogue-digital integrated circuits; spread spectrum communication; ΔΣ modulation; 0.35 micron; 2 V; 3.7 mW; DLL; DS-CDMA demodulator; IMT-2000; PN sequence; auxiliary ADC; delay locked-loop; double-metal double-poly CMOS process; dynamic range degradation; quantized correlation value; recycling integrator correlators; CMOS process; Correlators; Degradation; Delay; Delta modulation; Demodulation; Dynamic range; Multiaccess communication; Recycling; Voltage;
Conference_Titel :
Custom Integrated Circuits Conference, 2000. CICC. Proceedings of the IEEE 2000
Conference_Location :
Orlando, FL
Print_ISBN :
0-7803-5809-0
DOI :
10.1109/CICC.2000.852613
