Title :
A fabrication method for high performance embedded DRAM of 0.18 μm generation and beyond
Author :
Yoshida, T. ; Takato, H. ; Sakurai, T. ; Kokubun, K. ; Hiyama, K. ; Nomachi, A. ; Takasu, Y. ; Kishida, M. ; Ohtsuka, H. ; Naruse, H. ; Morimasa, Y. ; Yanagiya, N. ; Hashimoto, T. ; Noguchi, T. ; Miyamae, T. ; Iwabuchi, N. ; Tanaka, M. ; Kumagai, J. ; Ish
Author_Institution :
ULSI Device Eng. Lab., Toshiba Corp., Yokohama, Japan
Abstract :
A new fabrication method for embedded DRAM of 0.18 μm generation is proposed, which realizes full compatibility with logic process such as Co salicide, dual work function gate, small thermal budget and metalization, and introduces Self-aligned Salicide Block (SSB), a new process technology. Fabricated embedded DRAM shows excellent characteristics with respect to both retention time and MOSFET AC/DC performance, promising high performance of SOC (System On a Chip) applications
Keywords :
CMOS memory circuits; DRAM chips; application specific integrated circuits; integrated circuit technology; random-access storage; 0.18 micron; CoSi2; MOSFET AC/DC performance; SOC applications; dynamic RAM; fabrication method; high performance embedded DRAM; logic process compatibility; retention time; self-aligned salicide block process technology; system-on-a-chip applications; Capacitors; Fabrication; Logic arrays; Logic circuits; MOSFET circuits; Merging; Random access memory; Silicidation; Thermal degradation; Voltage;
Conference_Titel :
Custom Integrated Circuits Conference, 2000. CICC. Proceedings of the IEEE 2000
Conference_Location :
Orlando, FL
Print_ISBN :
0-7803-5809-0
DOI :
10.1109/CICC.2000.852618
