Mathematical analysis & model of packet delay variation experienced by IEEE 1588 packets

The IEEE1588 precision time protocol clock recovery algorithm is sensitive to Packet Delay Variation. The Packet Delay Variation can cause jitter/wander in recovered clock. Also accuracy of phase recovery and time it takes for PTP servo to acquire the phase lock, is dependent on the percentage of packets that fall inside the “floor window” or Floor Packet Percentage. So it is important to understand the characteristics of delay, one can expect for 1588 packets, when they pass through the network between 1588 Master and Slave. This paper proposes mathematical methods to analyze different delay characteristics such as lower and upper bounds on delays, probability distribution of the delays etc. The paper also shows how the delay probability of 1588 packets change when the number of links between master & slave or when percentage of load on these links changes. Output of a simple program which implements these methods is also given. The article shows that even with the best possible QOS treatment given to 1588 packets, which is strict priority scheduling at egress of each intermediate node, just changes in the load on the links can greatly affect Floor Packet Percentage and distribution of delay in general.