Cooperative caching in power-aware chip-multiprocessors

Chip-multiprocessors (CMPs) are emerging as a dominant architectural choice for both high-end (e.g., server machines) and low-power systems (e.g., mobile devices, laptops). The CMP system consists of several processors cores connected to their respective multi-level cache memories. Recently, some researchers proposed the concept of ldquocooperative cachingldquo to make the best use of aggregate cache resources available in the system. However, there are several inter-related issues that need to be investigated in order to get the full benefits of cooperative caching. The issues include the cache coherence at multi-level cache hierarchy, data replication, placement of shared data, and the support for low-power operation, among others. This paper outlines the working of a cache coherence protocol that supports cooperative caching in a power-aware CMP system. The paper also presents the framework of an analytical model to evaluate such cooperative caching strategies.