NV-SRAM: a nonvolatile SRAM with back-up ferroelectric capacitors

Author

Miwa, Tohm ; Yamada, Junichi ; Koike, Hiroki ; Toyoshima, Hideo ; Amanuma, Kazushi ; Kobayashi, Sota ; Tatsumi, Tom ; Maejima, Yukihiro ; Hada, Hiromitsu ; Kunio, Takemitsu

Author_Institution

Silicon Syst. Res. Labs., NEC Corp., Sagamihara, Japan

fYear

2000

fDate

2000

Firstpage

65

Lastpage

68

Abstract

This paper demonstrates new circuit technologies that enable a 0.25-μm ASIC SRAM macro to be nonvolatile with only a 17% cell area overhead (NV-SRAM: nonvolatile SRAM). New capacitor-on-metal/via-stacked-plug process technologies make it possible for a NV-SRAM cell to consist of a six-transistor ASIC SRAM cell and two back-up ferroelectric capacitors stacked over the SRAM portion. A Vdd/2 plate line architecture makes read/write fatigue virtually negligible. A 512-byte test chip has been successfully fabricated to show compatibility with ASIC technologies

Keywords

CMOS memory circuits; SRAM chips; application specific integrated circuits; ferroelectric capacitors; ferroelectric storage; integrated circuit layout; 0.25 micron; 512 byte; ASIC SRAM macro; NV-SRAM cell; Vdd/2 plate line architecture; back-up ferroelectric capacitors; capacitor-on-metal/via-stacked-plug process; circuit technologies; nonvolatile SRAM; six-transistor ASIC SRAM cell; Application specific integrated circuits; Capacitors; Electrodes; Emergency power supplies; Ferroelectric materials; Nonvolatile memory; Polarization; Random access memory; Read-write memory; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference, 2000. CICC. Proceedings of the IEEE 2000

Conference_Location

Orlando, FL

Print_ISBN

0-7803-5809-0

Type

conf

DOI

10.1109/CICC.2000.852619

Filename

852619