DocumentCode :
2157832
Title :
Modular test generation and concurrent transparency-based test translation using gate-level ATPG
Author :
Makris, Yiorgos ; Orailoglu, Alex ; Vishakantaiah, Praveen
Author_Institution :
Dept. of Comput. Sci. & Eng., California Univ., San Diego, La Jolla, CA, USA
fYear :
2000
fDate :
2000
Firstpage :
75
Lastpage :
78
Abstract :
We introduce a hierarchical test generation methodology for modular designs, employing exclusively gate-level ATPG. Based on the notion of modular transparency, the search space of the design is reduced to alleviate the complexity of gate-level test generation. Although ATPG is applied at the full circuit, faults in each module are targeted individually, while the surrounding modules are replaced by their much simpler, transparency-equivalent logic. As analyzed theoretically and as demonstrated through a set of experimental data, the proposed methodology results in significant test generation speed-up, while preserving comparable fault coverage and vector count to full-circuit gate-level ATPG
Keywords :
automatic test pattern generation; integrated circuit testing; logic testing; concurrent transparency-based test translation; design search space reduction; fault coverage; gate-level ATPG; gate-level test generation; hierarchical test generation methodology; modular designs; modular test generation; test generation speed-up; vector count; AC generators; Automatic test pattern generation; Circuit faults; Circuit testing; Design methodology; Genetics; Logic circuits; Logic testing; Performance evaluation; Time to market;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Custom Integrated Circuits Conference, 2000. CICC. Proceedings of the IEEE 2000
Conference_Location :
Orlando, FL
Print_ISBN :
0-7803-5809-0
Type :
conf
DOI :
10.1109/CICC.2000.852621
Filename :
852621
Link To Document :
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