A 500 MS/s 76dB SNDR continuous time delta sigma modulator with 10MHz signal bandwidth in 0.18μm CMOS

Author

Kaald, Rune ; Hernes, Bjornar ; Holdo, Christian ; Telsto, Frode ; Lokken, Ivar

Author_Institution

Dept. of Electron. & Telecommun., Norwegian Univ. of Sci. & Technol., Trondheim, Norway

fYear

2013

fDate

22-25 Sept. 2013

Firstpage

1

Lastpage

4

Abstract

A 5^th order continuous time delta sigma modulator is designed in 0.18μm CMOS. At a sampling rate of 500MHz it achieves 76dB SNDR over a 10MHz bandwidth consuming 58mW. 5^th order noiseshaping is realized with 4 opamp based RC integrators and a VCO realizing an integrator and a 4 bit quantizer. A THD of -82.3dBc is achieved without calibration of feedback DACs. A high speed capacitive implementation of excess loop delay compensation, together with a method for reducing the switching activity of the output codes from the VCO are proposed.

Keywords

CMOS analogue integrated circuits; compensation; continuous time systems; delta-sigma modulation; harmonic distortion; operational amplifiers; signal sampling; voltage-controlled oscillators; 5^th order continuous time delta sigma modulator; 5^th order noiseshaping; CMOS; SNDR continuous time delta sigma modulator; THD; VCO; bandwidth 10 MHz; bit quantizer; excess loop delay compensation; feedback DAC; high speed capacitive implementation; opamp based RC integrators; output codes; sampling rate; signal bandwidth; size 0.18 mum; switching activity; word length 4 bit; Bandwidth; Delays; Modulation; Noise; Resistors; Switches; Voltage-controlled oscillators;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference (CICC), 2013 IEEE

Conference_Location

San Jose, CA

Type

conf

DOI

10.1109/CICC.2013.6658527

Filename

6658527