Title :
Cell characterization for noise stability
Author :
Shepard, K.L. ; Chou, K.
Author_Institution :
Dept. of Electr. Eng., Columbia Univ., New York, NY, USA
Abstract :
Verifying whether a digital standard-cell design is functional in the presence of interconnect coupling noise is an important concern to ASIC designers. Determining whether the coupling noise occurring on a node is excessive requires comparing this noise against the dynamic noise margins of the receiving gates. The noise stability requirement, introduced in the context of transistor-level static noise analysis, is a technique for quantifying these AC noise margins. In this paper, we describe a technique for modelling noise stability in the form of a four-parameter rule which can be used to characterize the cells of a digital standard-cell library
Keywords :
application specific integrated circuits; circuit stability; digital integrated circuits; equivalent circuits; integrated circuit design; integrated circuit modelling; integrated circuit noise; AC noise margins; ASIC design; cell characterization; digital standard-cell design; digital standard-cell library; dynamic noise margins; four-parameter rule; interconnect coupling noise; noise stability modelling; transistor-level static noise analysis; Circuit noise; Circuit stability; Integrated circuit interconnections; Integrated circuit noise; Inverters; Laboratories; Logic gates; Pulse circuits; Stability analysis; Time domain analysis;
Conference_Titel :
Custom Integrated Circuits Conference, 2000. CICC. Proceedings of the IEEE 2000
Conference_Location :
Orlando, FL
Print_ISBN :
0-7803-5809-0
DOI :
10.1109/CICC.2000.852625
