All-digital 90° phase-shift DLL with a dithering jitter suppression scheme

Author

Dong-Hoon Jung ; Kyungho Ryu ; Jung-Hyun Park ; Won Lee ; Seong-Ook Jung

Author_Institution

Sch. of Electr. & Electron. Eng., Yonsei Univ., Seoul, South Korea

fYear

2013

fDate

22-25 Sept. 2013

Firstpage

1

Lastpage

4

Abstract

We propose a 90° phase-shift digital delay-locked loop (DLL) with a new dithering jitter suppression scheme. Delay-line control code dithering is effectively suppressed by comparing the distribution of the input and the output clock jitter. The proposed scheme is analyzed through a stochastic calculation. A test chip is fabricated using a 45-nm CMOS technology, and a 1.95-ps rms and 12.89-ps peak-to-peak jitter are achieved at 800-MHz operating frequency with a 1.1-V supply voltage. The measured power consumption is 1.32 mW at 800 MHz, and the active chip area is 69.9 μm x 49.3 μm.

Keywords

CMOS integrated circuits; clocks; delay lock loops; jitter; phase shifters; stochastic processes; 90° phase-shift DLL; CMOS technology; all-digital DLL; delay line control code dithering; delay locked loop; dithering jitter suppression scheme; frequency 800 MHz; input clock jitter; output clock jitter; power 1.32 mW; size 45 nm; size 49.3 mum; size 69.9 mum; stochastic calculation; time 1.95 ps; time 12.89 ps; voltage 1.1 V; Clocks; Delay lines; Delays; Frequency conversion; Jitter; Ring oscillators;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference (CICC), 2013 IEEE

Conference_Location

San Jose, CA

Type

conf

DOI

10.1109/CICC.2013.6658534

Filename

6658534