Power analysis of Input-Queued and Crosspoint-Queued crossbar switches

Crossbar switches are fundamental building blocks of digital networks such as the Internet. An input-queued (IQ) crossbar switch includes a set of queues at the input side of the switch, combined with an unbuffered switching matrix with N² crosspoints. A crosspoint-queued (XQ) crossbar switch contains a FIFO queue at each of the NxN crosspoints of the switching matrix. Switches with combined IQs and XQs, denoted CIXQ, have been the subject of considerable research over the last decade. The use of crosspoint queues simplifies the scheduling of traffic through the switch, at the cost of adding O(N²)FIFO queues to the switching matrix. In this paper, a power analysis of IQ and CIXQ switches is presented, assuming an FPGA implementation. The basic switch design consists of a demultiplexer network associated with each row of the switching matrix, and a multiplexer network associated with each column of the matrix. An accurate power analysis for these switches in an FPGA environment is presented. Analysis indicates that the internal FIFO queues in a CIXQ switch roughly triple the power required in an FPGA implementation. To minimize power, the FIFO queues at each crosspoint should be small or eliminated completely. The analytic models allows for a rapid design space exploration for power minimization.