A million gate PLD with 622 MHz I/O interface, multiple PLLs and high performance embedded CAM

Author

Cheung, Sammy ; Chua, Kar Keng ; Ang, Boon Jin ; Chong, Thow Pang ; Goay, Wei Lian ; Koay, Wei Yee ; Kuan, Sin WO ; Lim, Chooi Pei ; Oon, Jiunn Shyong ; See, Theam Thye ; Sung, Chiakang ; Tan, Kim Pin ; Tan, Yu Fong ; Wong, Choong Kit

Author_Institution

Altera Corp., San Jose, CA, USA

fYear

2000

fDate

2000

Firstpage

143

Lastpage

146

Abstract

A million gate programmable logic device (PLD) designed for high performance system integration is discussed. The APEX 20K1000E is fabricated on a 0.18 μm CMOS process. The chip supports multiple I/O standards with data bandwidth up to 622 Mbps when using the integrated low voltage differential signaling (LVDS) interfaces. Multiple on-chip phase-locked loops (PLL) increase performance and provide clock-frequency synthesis. The embedded content addressable memory (CAM) enhances performance for fast search applications

Keywords

CMOS logic circuits; clocks; content-addressable storage; digital phase locked loops; programmable logic devices; 0.18 micron; 622 MHz; 622 Mbit/s; APEX 20K1000E; CMOS process; I/O interface; PLD; clock-frequency synthesis; data bandwidth; embedded CAM; embedded content addressable memory; fast search applications; low voltage differential signaling; multiple I/O standards; multiple PLLs; multiple on-chip phase-locked loops; system integration; Associative memory; Bandwidth; CADCAM; CMOS process; Clocks; Computer aided manufacturing; Low voltage; Phase locked loops; Programmable logic devices; Signal synthesis;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference, 2000. CICC. Proceedings of the IEEE 2000

Conference_Location

Orlando, FL

Print_ISBN

0-7803-5809-0

Type

conf

DOI

10.1109/CICC.2000.852636

Filename

852636