DocumentCode
2158299
Title
A general-purpose vision processor with 160×80 pixel-parallel SIMD processor array
Author
Lopich, Alexey ; Dudek, Piotr
Author_Institution
Sch. of Electr. & Electron. Eng., Univ. of Manchester, Manchester, UK
fYear
2013
fDate
22-25 Sept. 2013
Firstpage
1
Lastpage
4
Abstract
In this paper we present a vision processor, which incorporates a 160×80 SIMD array of pixel-processors. The processor operates with a 100MHz clock and 1.8V supply. The device provides 640 GOPS (binary) and 23 GOPS (greyscale) consuming 0.5 W. The chip occupies 50mm2 and is fabricated in a standard 0.18 μm CMOS process. The I/O interface supports 200 MPixels/s (greyscale), 1.6 GPixels/s (binary) and 40 MPixels/s (address-event readout) data rate, and PE-parallel image sensing mode for embedded high-speed vision applications. Experimental results indicate that the performance of the presented chip approaches the efficiency of recently reported application-specific vision processors, while providing full programmability and thus being adjustable to a wide range of applications.
Keywords
computer vision; microprocessor chips; parallel processing; I/O interface; PE-parallel image sensing; address-event readout; general-purpose vision processor; high-speed vision applications; pixel-parallel SIMD processor array; Arrays; Clocks; Image processing; Microprocessors; Ports (Computers); Registers;
fLanguage
English
Publisher
ieee
Conference_Titel
Custom Integrated Circuits Conference (CICC), 2013 IEEE
Conference_Location
San Jose, CA
Type
conf
DOI
10.1109/CICC.2013.6658542
Filename
6658542
Link To Document