Evaluation of defect-tolerance scheme in a 600 M-bit wafer-scale memory

Describes a simulator using Monte Carlo simulation that has been used to evaluate the defect tolerance scheme in 600 M-bit wafer-scale DRAM having additional switching register network logic (SW-REG). To obtain functional wafers even if a memory core yield is as low as 5%, a bypass line for SW-REG and spare lines for common signals are prepared, and the number of sections that the memory is to be partitioned into is determined. One can obtain about 300 to 650 M bits on a 6-in wafer when the memory core yield is 5 to 70%. Although the wafer-scale memory has hundreds of common signal lines because of parallel access, one can have an area-efficient system with optimized additional circuits using the simulator