A 1Gb/s reconfigurable pulse compression radar signal processor in 90nm CMOS

Author

Li, Jie ; Mukai, Hiroaki ; Parlak, Mehmet ; Matsuo, Michiaki ; Buckwalter, James F.

Author_Institution

Univ. of California-San Diego, La Jolla, CA, USA

fYear

2013

fDate

22-25 Sept. 2013

Firstpage

1

Lastpage

4

Abstract

This paper presents a reconfigurable analog signal processing circuit for pulse compression radar. Adapting bandwidth for the range of the target is proposed for radar systems. The baseband signal processor includes a high-speed correlator/integrator, a 4-bit flash analog-to-digital converter (ADC) and a multi-range delay lock loop (DLL). The DLL generates multi-phase clock to align the template signal with the received signal. The circuit is fabricated in 90-nm CMOS and can be configured to work from 50Mb/s to 1Gb/s with Barker codes. A sidelobe reduction (SLR) of 15.6dB is demonstrated for 1Gb/s. The total power consumption is 33mW at 1Gb/s.

Keywords

CMOS integrated circuits; analogue-digital conversion; correlators; delay lock loops; pulse compression; radar signal processing; 4-bit flash analog-to-digital converter; ADC; Barker codes; DLL; SLR; baseband signal processor; bit rate 50 Mbit/s to 1 Gbit/s; high-speed correlator; high-speed integrator; multiphase clock; multirange delay lock loop; power 33 mW; pulse compression radar; reconfigurable analog signal processing circuit; sidelobe reduction; size 90 nm; word length 4 bit; CMOS integrated circuits; Correlation; Correlators; Signal resolution; Spaceborne radar;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference (CICC), 2013 IEEE

Conference_Location

San Jose, CA

Type

conf

DOI

10.1109/CICC.2013.6658545

Filename

6658545