A low-power CMOS super-regenerative receiver at 1 GHz

Author

Vouilloz, Alexandre ; Dehollain, Catherine ; Declercq, Michel

Author_Institution

Electron. Lab., Swiss Fed. Inst. of Technol., Lausanne, Switzerland

fYear

2000

fDate

2000

Firstpage

167

Lastpage

170

Abstract

A low-power and low-voltage super-regenerative receiver operating at 1 GHz and implemented in a 0.35 μm CMOS process is described. The receiver includes a LNA, a super-regenerative oscillator, an envelope detector, AGC circuitry with sample/hold capability and a baseband amplifier. The die-surface is equal to 0.25 mm². An overall noise figure of 14.7 dB is achieved. The power consumption is less than 1.2 mW at V_DD=1.5 V. A 100 kHz saw tooth quench signal has been used to achieve an interferer rejection of -35.9 dB at 500 kHz from the center frequency

Keywords

CMOS analogue integrated circuits; UHF integrated circuits; application specific integrated circuits; low-power electronics; radio receivers; 0.35 micron; 1 GHz; 1.2 mW; 1.5 V; 14.7 dB; AGC circuitry; ASIC; LNA; baseband amplifier; envelope detector; low-power CMOS receiver; low-voltage operation; sample/hold capability; super-regenerative oscillator; super-regenerative receiver; CMOS technology; Demodulation; Energy consumption; Envelope detectors; Feedback loop; Frequency; Impedance; Laboratories; Oscillators; Transconductance;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference, 2000. CICC. Proceedings of the IEEE 2000

Conference_Location

Orlando, FL

Print_ISBN

0-7803-5809-0

Type

conf

DOI

10.1109/CICC.2000.852641

Filename

852641