New paradigm of predictive MOSFET and interconnect modeling for early circuit simulation

Author

Cao, Yu ; Sato, Takashi ; Orshansky, Michael ; Sylvester, Dennis ; Hu, Chenming

Author_Institution

Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA

fYear

2000

fDate

2000

Firstpage

201

Lastpage

204

Abstract

A new paradigm of predictive MOSFET and interconnect modeling is introduced. This approach is developed to specifically address SPICE compatible parameters for future technology generations. For a given technology node, designers can use default values or directly input L _eff, T_ok, V_t, R_dsw and interconnect dimensions to instantly obtain a BSIM3v3 customized model for early stages of circuit design and research. Models for 0.18 μm and 0.13 μm technology nodes with L_eff down to 70 nm are currently available on the web. Comparisons with published data and 2D simulations are used to verify this predictive technology model

Keywords

CMOS integrated circuits; MOS integrated circuits; MOSFET; SPICE; circuit simulation; integrated circuit interconnections; integrated circuit modelling; semiconductor device models; 0.13 micron; 0.18 micron; 70 nm; BSIM3v3 customized model; SPICE compatible parameters; early circuit simulation; predictive MOSFET modeling; predictive interconnect modeling; predictive technology model; Capacitance; Circuit simulation; Circuit synthesis; Computational modeling; Computer simulation; Integrated circuit interconnections; Integrated circuit modeling; MOSFET circuits; Predictive models; SPICE;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference, 2000. CICC. Proceedings of the IEEE 2000

Conference_Location

Orlando, FL

Print_ISBN

0-7803-5809-0

Type

conf

DOI

10.1109/CICC.2000.852648

Filename

852648