A hierarchical decomposition methodology for single-stage clock circuits

This paper describes a methodology for designing the interconnect distribution for single-stage clock circuits using a hierarchical decomposition. This new method of splitting the design into global and local distributions improves the optimization efficiency and enhances both wireability and performance. A novel use of the Delaunay triangulation provides a means for efficiently constructing and optimizing the local distribution. The combination of these global and local solutions produces layouts with less wirelength and an average 3× performance improvement over flat solutions while keeping the worst case skew below 50 ps. When these designs are wiresized, they achieve a 25% reduction in wire area over their flat circuit counterparts due to the reduction in downstream capacitive wire loading