A novel process-controlled-monitor structure suitable for RF CMOS characterization

A novel layout design for process monitoring test structure of RF MOSFET has been proposed in this paper. The test structure consumes only 62% area of the conventional structure and can be easily inserted into the scribe-line of individual chips. The proposed structure is very suitable for in-process electrical testing including BC, CV, and RF characterization. And this new layout test structure also can be extended to other DUT measurements, for example, capacitor, diode, varactor, and interconnects.