DocumentCode
2158884
Title
A highly linear low-power 10 bit DAC for GSM
Author
Ferguson, Paul F., Jr. ; Haurie, Xavier ; Temes, Gabor C.
Author_Institution
Analog Devices Inc., Wilmington, MA, USA
fYear
2000
fDate
2000
Firstpage
261
Lastpage
264
Abstract
A 10-bit 6.5 MS/s DAC designed for a GSM baseband transmit channel is described. It features a low power quasipassive architecture with segmentation and element mismatch-shaping used in the conversion of the four MSBs. The DAC charge is entered into an integrated switched-capacitor biquad filter with passive charge sharing in the output stage, which passes the signal to a continuous time output stage. The DAC achieves less than 1/4 bit DNL and 0.6 bit INL at the 10-bit level with no calibration or trimming
Keywords
biquadratic filters; cellular radio; digital-analogue conversion; low-power electronics; switched capacitor filters; 10 bit; GSM; baseband transmit channel; continuous time output stage; element mismatch-shaping; integrated switched-capacitor biquad filter; linear DAC; low-power electronics; passive charge sharing; quasipassive architecture; segmentation; Baseband; Calibration; Capacitors; Digital modulation; Filtering; GSM; Passive filters; Pipelines; Telephone sets; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Custom Integrated Circuits Conference, 2000. CICC. Proceedings of the IEEE 2000
Conference_Location
Orlando, FL
Print_ISBN
0-7803-5809-0
Type
conf
DOI
10.1109/CICC.2000.852662
Filename
852662
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