Title :
Multiple voting systolic array
Author :
Mori, Hideki ; Kambara, Junichi
Author_Institution :
Dept. of Inf. & Comput. Sci., Toyo Univ., Kawagoe, Japan
Abstract :
A model of the multiple voting systolic array is proposed. The proposed fault tolerant technique uses majority decision by voting, without reconfiguration. As an example, a DFT (discrete Fourier transform) implementation of a triple voting systolic array is presented. It is shown that area redundancy is small and dynamic fault recovery is possible. It is believed that proposed fault-tolerant architecture is suitable for WSI (wafer-scale integration) processors
Keywords :
VLSI; fast Fourier transforms; fault tolerant computing; microprocessor chips; systolic arrays; DFT; WSI; area redundancy; dynamic fault recovery; fault tolerant technique; majority decision; model; multiple voting systolic array; Computer architecture; Concurrent computing; Fault tolerance; Hardware; High performance computing; Parallel processing; Pipeline processing; Redundancy; Systolic arrays; Voting;
Conference_Titel :
Wafer Scale Integration, 1991. Proceedings., [3rd] International Conference on
Conference_Location :
San Francisco, CA
Print_ISBN :
0-8186-9126-3
DOI :
10.1109/ICWSI.1991.151692
