Title :
An ultra-high-density high-speed loadless four-transistor SRAM macro with a dual-layered twisted bit-line and a triple-well shield
Author :
Noda, K. ; Matsui, K. ; Ito, S. ; Masuoka, S. ; Kawamoto, H. ; Ikezawa, N. ; Takeda, K. ; Aimoto, Y. ; Nakamura, N. ; Toyoshima, H. ; Iwasaki, T. ; Horiuchi, T.
Author_Institution :
ULSI Device Dev. Lab., NEC Corp., Sagamihara, Japan
Abstract :
We have developed two schemes for improving access speed and reliability of a loadless four-transistor (4T) SRAM cell: a dual-layered twisted bit line, which reduces coupling capacitance between adjacent bit lines in order to achieve high-speed read/write operations; and triple-well shielding, which protects the memory cell from substrate noise and alpha particles. We incorporated these technologies in a 0.18-μm CMOS process and fabricated a 16-Mb SRAM macro with a 1.9-μ2 memory cell. This macro fully functions at 400 MHz and has an access time of 2.35 ns
Keywords :
CMOS memory circuits; SRAM chips; high-speed integrated circuits; integrated circuit reliability; memory architecture; radiation hardening (electronics); 0.18 micron; 16 Mbit; 2.35 ns; 400 MHz; CMOS process; access speed; access time; adjacent bit lines; alpha particle protection; coupling capacitance; dual-layered twisted bit-line; high-speed circuits; loadless four-transistor SRAM macro; read/write operations; reliability; substrate noise; triple-well shield; ultra-high-density circuits; CMOS process; CMOS technology; Capacitance; Equivalent circuits; Laboratories; MOSFETs; National electric code; Noise reduction; Random access memory; Writing;
Conference_Titel :
Custom Integrated Circuits Conference, 2000. CICC. Proceedings of the IEEE 2000
Conference_Location :
Orlando, FL
Print_ISBN :
0-7803-5809-0
DOI :
10.1109/CICC.2000.852667
