Design validation of .18 μm 1 GHz cache and register arrays

Author

Malone, Doug ; Bunce, Paul ; DellaPietro, Joe ; Davis, John ; Dawson, Jim ; Knips, Tom ; Plass, Don ; Pritzlaff, Phil ; Reyer, Ken

Author_Institution

IBM Corp., Poughkeepsie, NY, USA

fYear

2000

fDate

2000

Firstpage

295

Lastpage

298

Abstract

This paper describes the design and results of SRAM experiments from a prototype test chip in IBM´s .18 μm 7 level metal copper technology. Results and approaches for assuring product applications at 1 GHz across wide process ranges will be discussed. Aggressive product cycle time SRAM applications for IBM´s S/390 L2 cache chips require multifaceted approaches to address the following: (a) SRAM operability in product-like clocking and ABIST environments, (b) Demonstration of yield using 2 dimensional redundancy, (c) Characterization of SRAM signals used in the macro timing rules, (d) Obtain high volume pre-product manufacturing test data, (e) Verify SRAM functionality at technology stress test conditions

Keywords

SRAM chips; built-in self test; cache storage; cellular arrays; integrated circuit testing; redundancy; timing; 0.18 micron; 1 GHz; ABIST environment; S/390 L2 cache chips; SRAM; macro timing rules; multifaceted approaches; pre-product manufacturing test data; product applications; product cycle time; register arrays; technology stress test conditions; two-dimensional redundancy; Circuit testing; Clocks; Copper; Delay; Logic arrays; Logic testing; Prototypes; Random access memory; Registers; Timing;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference, 2000. CICC. Proceedings of the IEEE 2000

Conference_Location

Orlando, FL

Print_ISBN

0-7803-5809-0

Type

conf

DOI

10.1109/CICC.2000.852670

Filename

852670