A single chip 155 Mbps/140 Mbps SDH/PDH transceiver

Author

Guinea, Jesus ; Tomasini, Luciano ; Maggio, Santo ; Rutar, Massimiliano

Author_Institution

ST Microelectron., Agrate, Italy

fYear

2000

fDate

2000

Firstpage

315

Lastpage

318

Abstract

The 155 Mbps (STM-l electrical) transceiver complies with the relevant ITU-T recommendations. The transmit channel features CMI transmission (transformerless) with specified jitter-generation. On the receiver side, jitter-tolerance and bit error rate performance is attained. A cable equalizer supports 13.7 dB loss (Nyquist-frequency) and has an eye-closure less than 600 psec. The device uses one master-clock (155 MHz) and a DLL for both TX and RX synchronization. Targeted crosstalk isolation performance is achieved with a 0.35 μm BiCMOS technology. The TQFP48 IC powered from 3.3 V consumes 390 mW

Keywords

BiCMOS integrated circuits; broadband networks; crosstalk; digital communication; jitter; mixed analogue-digital integrated circuits; synchronisation; synchronous digital hierarchy; transceivers; 0.35 micron; 13.7 dB; 155 MHz; 3.3 V; 390 mW; ASIC; BER performance; BiCMOS technology; CMI transmission; DLL; ITU-T recommendations; STM-l; TQFP48 package; bit error rate; cable equalizer; crosstalk isolation performance; jitter tolerance; master-clock; receiver; single chip SDH/PDH transceiver; specified jitter generation; synchronization; transmit channel; Clocks; Crosstalk; Driver circuits; Integrated circuit noise; Jitter; Phase locked loops; Synchronization; Synchronous digital hierarchy; Timing; Transceivers;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference, 2000. CICC. Proceedings of the IEEE 2000

Conference_Location

Orlando, FL

Print_ISBN

0-7803-5809-0

Type

conf

DOI

10.1109/CICC.2000.852675

Filename

852675