A 450 Mbit/s parallel read/write channel with parity check and 16-state time variant Viterbi

Author

Bollati, G. ; Dati, A. ; Betti, G. ; Bietti, I. ; Brianti, F. ; Bruccoleri, M. ; Coltella, M. ; Demartini, P. ; Demicheli, M. ; Gadducci, P. ; Marchese, S. ; Ottini, D. ; Pisati, V. ; Rezzi, F. ; Rossi, A. ; Savo, P. ; Tonci, C. ; Castello, R.

Author_Institution

STMicroelectron., Italy

fYear

2000

fDate

2000

Firstpage

319

Lastpage

322

Abstract

A PRML read/write IC operating up to 450 Mbit/s is presented. The chip implements a 16-state EPR4 parity check time variant Viterbi detector and a digital servo. A 24/26 code with parity check improves the robustness to white noise, media noise and to off-track conditions. The device is integrated in a mature 0.35 μm BiCMOS technology with a die size of 13 mm² (step and repeat) and dissipates 1.9 W (in read mode) at 450 Mbit/s

Keywords

BiCMOS integrated circuits; Viterbi decoding; application specific integrated circuits; disc drives; hard discs; magnetic recording noise; maximum likelihood decoding; partial response channels; servomechanisms; white noise; 0.35 micron; 1.9 mW; 24/26 code; 450 Mbit/s; BiCMOS technology; EPR4; PRML; die size; digital servo; media noise; off-track conditions; parallel read/write channel; parity check; time variant Viterbi; white noise; Clocks; Delay; Finite impulse response filter; Frequency synthesizers; Low pass filters; Parity check codes; Ring oscillators; Servomechanisms; Viterbi algorithm; Voltage-controlled oscillators;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference, 2000. CICC. Proceedings of the IEEE 2000

Conference_Location

Orlando, FL

Print_ISBN

0-7803-5809-0

Type

conf

DOI

10.1109/CICC.2000.852676

Filename

852676