Author :
Bollati, G. ; Dati, A. ; Betti, G. ; Bietti, I. ; Brianti, F. ; Bruccoleri, M. ; Coltella, M. ; Demartini, P. ; Demicheli, M. ; Gadducci, P. ; Marchese, S. ; Ottini, D. ; Pisati, V. ; Rezzi, F. ; Rossi, A. ; Savo, P. ; Tonci, C. ; Castello, R.
Abstract :
A PRML read/write IC operating up to 450 Mbit/s is presented. The chip implements a 16-state EPR4 parity check time variant Viterbi detector and a digital servo. A 24/26 code with parity check improves the robustness to white noise, media noise and to off-track conditions. The device is integrated in a mature 0.35 μm BiCMOS technology with a die size of 13 mm2 (step and repeat) and dissipates 1.9 W (in read mode) at 450 Mbit/s
Keywords :
BiCMOS integrated circuits; Viterbi decoding; application specific integrated circuits; disc drives; hard discs; magnetic recording noise; maximum likelihood decoding; partial response channels; servomechanisms; white noise; 0.35 micron; 1.9 mW; 24/26 code; 450 Mbit/s; BiCMOS technology; EPR4; PRML; die size; digital servo; media noise; off-track conditions; parallel read/write channel; parity check; time variant Viterbi; white noise; Clocks; Delay; Finite impulse response filter; Frequency synthesizers; Low pass filters; Parity check codes; Ring oscillators; Servomechanisms; Viterbi algorithm; Voltage-controlled oscillators;
