DocumentCode :
2159211
Title :
Designing systolic arrays for integer GCD computation
Author :
Jebelean, Tudor
Author_Institution :
RISC-LINZ, Linz, Austria
fYear :
1994
fDate :
22-24 Aug 1994
Firstpage :
295
Lastpage :
301
Abstract :
We improve the classical result of Brent and Kung (1985) by a factor of 12 in area consumption, while maintaining the same average running time. Global broadcasting is eliminated using a novel technique which is more efficient then Leisersons (1982) semisystolic-to-systolic transformation and can be also applied to other arithmetic algorithms. Experiments using field programmable gate arrays demonstrate the possibility of speeding-up long integer arithmetic by two orders of magnitude by implementing this algorithm in dedicated hardware
Keywords :
logic arrays; parallel algorithms; special purpose computers; systolic arrays; area consumption; arithmetic algorithms; average running time; dedicated hardware; field programmable gate arrays; global broadcasting; greatest common divisor; integer GCD computation; integer arithmetic; semisystolic-to-systolic transformation; systolic array design; two orders of magnitude; Algebra; Application software; Broadcasting; Cryptography; Digital arithmetic; Europe; Field programmable gate arrays; Hardware; Registers; Systolic arrays;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Application Specific Array Processors, 1994. Proceedings. International Conference on
Conference_Location :
San Francisco, CA
ISSN :
1063-6862
Print_ISBN :
0-8186-6517-3
Type :
conf
DOI :
10.1109/ASAP.1994.331795
Filename :
331795
Link To Document :
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