Synthesis of a class of data format converters with specified delays

We propose a design methodology for synthesis of a special class of Data Format Converters (DFCs) in which the site of I/O sequences and the delays between I/O sequences are specified. The need for such DFCs arises in many signal and image processing applications. Our DFCs are based on a two-dimensional architecture. The designs using our methodology have maximum throughput rate and are area-efficient. A VLSI architecture for computing the discrete wavelet transform is given as an example to illustrate the proposed design methodology. The design of a Zig-zag Scanner is also given. For several representative problems, the area requirements of our designs are compared against those obtained by earlier design methodologies. For all the problems considered, our methodology leads to compact designs